1. Field of the Invention
The present invention relates to a bistable circuit, and more particularly to a bistable circuit capable of stably operating even if a data signal is out of time with a clock signal.
2. Description of relates art
Bistable circuits alternatively assume two stable conditions in response to two inputs. Namely, if a signal is applied to a first input, the bistable circuit is brought into a first stable condition until a signal is applied to a second input. The two stable conditions of the bistable circuits can be regarded to correspond to binary information "0" and "1", respectively. Therefore, the bistable circuits have been used in various digital circuits such as counters, shift registers, and the likes. These bistable circuits are mainly divided into two types, i.e., the asynchronous type and the synchronous type. In the asynchronous bistable circuits, the application of an input signal triggers the bistable circuit immediately. On the other hand, in the synchronous type, changes of state will occur only at selected times, i.e., when or after a clock signal is applied.
In the case of a plurality of asynchronous bistable circuits being used, uncontrolled delays are inevitable, although individually very small (typically of the order of a few nanoseconds), and these delays will introduce differential delays between signals that must travel through different numbers of logic circuits. Unwanted signal combinations may therefore appear for short periods and may be interpreted erroneously.
The synchronous bistable circuits do not suffer from such a problem, because they conform to the control signals only when the clock signal is present. Therefore, the synchronous bistable circuits are widely used in logical circuits.
However, the synchroneous bistable circuits involve another problem in which the outputs take an intermediate potential when the transistion of a data signal encounters the transition of a clock signal. If such an intermediate potential is outputted to the next bistable circuit, the state of the next circuit is not determined, which would result in malfunction of a circuit including the bistable circuits.